1. Field of the Invention
The present invention relates silicon controlled rectifiers, SCRs, and more particularly to SCRs with controlled triggering and holding voltages.
2. Background Information
Protecting circuits from electrostatic discharges, where the protection is on the chip is an essential component for integrated circuits, especially newer, faster, smaller designs often found in very large scale integration, VLSI, circuits.
FIG. 1 illustrates a traditional bipolar SCR protection device. This device may be fabricated using standard MOS processes (hence the “gate” terminal), where the bipolar transistors are often labeled as parasitic, but it is these transistors which provide the protection. Often there are resistors from the anode to the base, R1, of T1 and one from the gate to the cathode, R2. If the gate and the cathode are at ground, the anode may rise in voltage with nothing happening but some small leakage current until the device breaks down. If a separate signal is developed that forward biases the gate to cathode, T2 will turn on which in turn turns on T1 and the device triggers presenting a low impedance from the anode to the cathode. However, it would be advantageous to not to supply this separate signal.
If the gate remains unconnected, and the voltage, VA, at the anode rises with VB at ground, VA will reach a trigger (or snap-back) voltage level, VAB, that will produce the negative resistance snap-back curve shown in FIG. 2. VA falls to the holding voltage, VH. When VAB is reached, T1 or T2 may break down and turn on the other. The net effect is that the device triggers, then T1 and T2 turn on presenting a low impedance from anode to cathode. This condition is sometimes referred to “latch up.” Typically the current is limited, so the latch-up is usually not destructive.
Known problems continue to exist in the prior art circuit. For example, with an SCR across a power rail, when an ESD (Electrostatic Discharge) event occurs, the SCR may turn on, but when the event ends, the SCR may remain on, if the power rail voltage is higher than the holding voltage of the SCR. Some known SCRs turn on at voltages that are too high to fully protect low voltage ICs (integrated circuits), e.g. circuits using 3.3V or 1.8V power supplies.
Typically models have been developed to gauge and classify ESD events. The peak voltages run from about ±0.5 kV to 16 kV. Some of these models are: the HBM (Human Body Model); the MM (Machine Model); the CDM (Charged Device Model); and the IEC (International Electrotechnical Commission) model. The ESD event times for these models run from about less than ten nanoseconds rise times and decay times of about ten times as long.
Regardless of their limitations, SCRs have been among the electronic components of choice for such protection and there are many examples in the prior art. Among that prior art are: U.S. Pat. No. 6,172,404 ('404) to Chen et al. that issued on Jan. 9, 2001; U.S. Pat. No. 7,071,528 ('528) to Ker et al. that issued on Jul. 4, 2006; U.S. patent publication no. 2005/0151160 ('160) to Salcedo et al. that issued on Jul. 14, 2005; and U.S. patent publication no. 2006/0151836 ('836) to Salcedo et al. that issued on Jul. 13, 2006.
The '404 patent is silent on the trigger voltage (anode to cathode) value that is a specific characteristic in the present invention. Moreover, the '404 does not suggest the low voltage triggering and relatively high holding voltage of the present invention.
The '528 patent incorporates a three terminal device with a separate trigger signal supplied to the equivalent of the gate terminal of FIG. 1. The present invention does not suggest a three terminal device.
The '160 and the '836 publications do not suggest a trigger voltage below +13V or 15V, respectively, as compared to the +8 V trigger voltage of the present invention.